Analysis and Simulation of Gate Leakage Current in P3 SRAM Cell at Deep-Sub-Micron Technology for Multimedia Applications
نویسندگان
چکیده
In this paper the gate leakage current analysis of the Conventional 6T SRAM, NC-SRAM, PP SRAM, and P3 SRAM cell has been carried out. It has been observed that due to pMOS stacking and direct supply body biasing in the P3 SRAM Cell, there is a reduction of gate leakage current 66.55%, 34.42%, and 90.99% with respect to the 6T, NC-Cell, and PP cell, respectively for VDD=0.8V. For VDD=0.7V, it is found 82.2%, 75.35%, and 93.15%, respectively. The total standby leakage power in P3 SRAM Cell is found significantly reduced by 69.07%, 13.61%, and 81.01% at VDD=0.8V and 73.07%, 16.79%, and 87.94% at V DD=0.7V, with respect to the Conventional 6T SRAM Cell, NC-SRAM Cell, and PP SRAM Cell. The simulation is being performed at tox =2.4nm, VDD = 0.8V and 0.7V, Vthn=0.22V, and Vthp=0.224V.
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